Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype

Omotosho, Adebayo, IIahi, Sirine, Villegas Castillo, Ernesto Cristopher, Hammer, Christian and Sauer, Christian (2023) Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype. In: 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE, pp. 1-6. ISBN 9798350332773

Text 15813 Omotosho A et al (2023) Evaluating_the_Hardware_Performance_Counters_of_an_Xtensa_Virtual_Prototype.pdf - Published Version Restricted to Repository staff only Available under License All Rights Reserved. Download (1MB)

Abstract

Embedded systems’ hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifiying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

Item Type:	Book Section
Uncontrolled Keywords:	Virtual prototype; Xtensa; Hardware performance counters; Return oriented programming; Machine learning
Divisions:	Schools and Research Institutes > School of Business, Computing and Social Sciences
Depositing User:	Kamila Niekoraniec
Date Deposited:	04 Feb 2026 10:51
Last Modified:	04 Feb 2026 11:00
URI:	https://eprints.glos.ac.uk/id/eprint/15813

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